This invention relates to integrated-circuit devices made in complementary-metal-oxide-semiconductor (CMOS) form and, more particularly, to a method for fabricating isolation trenches in such devices.
It is known to utilize dielectric-filled trenches in a CMOS device to achieve isolation between adjacent n-channel and p-channel transistor regions. In that way, latchup-free operation of a CMOS device can be ensured.
In a CMOS device utilizing trenches for isolation, inversion layers may form along the sidewalls of the trenches. Such layers can deleteriously affect device performance by causing transistors adjacent to the trenches to exhibit undesirably high leakage to the device substrate. In some cases, the sidewall inversion layers can actually lead to device failure by causing source/drain regions along the sidewalls to be shorted together.
Selectively doping the sidewalls has the potential to eliminate or substantially reduce inversion effects in a trench-isolated CMOS device. But such an approach, which requires that each sidewall of a trench be doped independently, is made exceedingly difficult by the extremely narrow and deep structure of typical trenches in a very-large-scale-integrated (VLSI) CMOS device. Available lithographic techniques, for example, are not feasible for selectively masking the sidewalls of such trenches to establish a basis for selective doping.
Efforts were therefore directed by workers skilled in the art aimed at trying to devise an effective approach for carrying out the aforespecified selective doping. It was recognized that such efforts, if successful, had the potential for making a significant contribution to the realization of a highly reliable latchup-free VLSI CMOS device of the trench-isolation type.